A novel parity bit lock-on circuit is disclosed in a copending patent application Ser. No. 311,783, filed concurrently herewith, by Charles S. Weaver and John M. Yarborough Jr., entitled Digital Data Transmission With Parity Bit Word Lock-On, which application is assigned to the assignee of the present invention. The parity bit lock-on circuit disclosed therein includes means for locking onto parity bits included in a serial bit stream consisting of equal length words, each of which words includes a parity bit. Word-length groups of bits of the bit stream are checked for parity at every bit interval of the stream. A shift register one word length in size is provided into which the output from the parity checker is shifted if the serial output from the register is a parity true signal. If the serial output from the shift register is a parity error signal, then a parity error signal is reentered into the shift register. Whenever the shift register contains parity error signals at all but one given register stage, a word clock is produced in synchronization with the parity bit in the serial word stream. Generally, parity bit lock-on is not achieved until a plurality of words have passed through the circuit which words are lost. The present invention is directed to means for reducing the number of words lost before parity bit lock-on.